; generated by Component: ARM Compiler 5.06 update 5 (build 528) Tool: ArmCC [4d3621]
; commandline ArmCC [--list --debug -c --asm --interleave -o.\obj\mdio.o --asm_dir=.\Obj\ --list_dir=.\Obj\ --depend=.\obj\mdio.d --cpu=Cortex-M3 --apcs=interwork -O3 --diag_suppress=9931 -I. -I.\Core_CM3 -IC:\Keil\ARM\RV31\INC -IC:\Keil\ARM\CMSIS\Include -IC:\Keil\ARM\INC\NXP -D__UVISION_VERSION=524 --omf_browse=.\obj\mdio.crf ethernet\mdio.c]
                          THUMB

                          AREA ||.text||, CODE, READONLY, ALIGN=2

                  output_MDIO PROC
;;;18     
;;;19     static void output_MDIO (U32 val, U32 n) {
000000  f1c10220          RSB      r2,r1,#0x20
;;;20     
;;;21        /* Output a value to the MII PHY management interface. */
;;;22        for (val <<= (32 - n); n; val <<= 1, n--) {
000004  4090              LSLS     r0,r0,r2
000006  b510              PUSH     {r4,lr}               ;19
;;;23           if (val & 0x80000000) {
;;;24              LPC_GPIO2->FIOSET = MDIO;
000008  4a35              LDR      r2,|L1.224|
00000a  f44f7400          MOV      r4,#0x200
;;;25           }
;;;26           else {
;;;27              LPC_GPIO2->FIOCLR = MDIO;
;;;28           }
;;;29           delay ();
;;;30           LPC_GPIO2->FIOSET = MDC;
00000e  1553              ASRS     r3,r2,#21
000010  e008              B        |L1.36|
                  |L1.18|
000012  2800              CMP      r0,#0                 ;23
000014  da01              BGE      |L1.26|
000016  6594              STR      r4,[r2,#0x58]         ;24
000018  e000              B        |L1.28|
                  |L1.26|
00001a  65d4              STR      r4,[r2,#0x5c]         ;27
                  |L1.28|
00001c  6593              STR      r3,[r2,#0x58]
;;;31           delay ();
;;;32           LPC_GPIO2->FIOCLR = MDC;
00001e  65d3              STR      r3,[r2,#0x5c]
000020  0040              LSLS     r0,r0,#1              ;22
000022  1e49              SUBS     r1,r1,#1              ;22
                  |L1.36|
000024  2900              CMP      r1,#0                 ;22
000026  d1f4              BNE      |L1.18|
;;;33        }
;;;34     }
000028  bd10              POP      {r4,pc}
;;;35     
                          ENDP

                  mdio_read PROC
;;;67     
;;;68     U32 mdio_read(int PhyReg) {
00002a  b570              PUSH     {r4-r6,lr}
;;;69        U32 val;
;;;70     
;;;71        /* Configuring MDC on P2.8 and MDIO on P2.9 */
;;;72        LPC_GPIO2->FIODIR |= MDIO;
00002c  4d2c              LDR      r5,|L1.224|
00002e  4604              MOV      r4,r0                 ;68
000030  6c28              LDR      r0,[r5,#0x40]
000032  f4407000          ORR      r0,r0,#0x200
000036  6428              STR      r0,[r5,#0x40]
;;;73     
;;;74        /* 32 consecutive ones on MDO to establish sync */
;;;75        output_MDIO (0xFFFFFFFF, 32);
000038  2120              MOVS     r1,#0x20
00003a  f04f30ff          MOV      r0,#0xffffffff
00003e  f7fffffe          BL       output_MDIO
;;;76     
;;;77        /* start code (01), read command (10) */
;;;78        output_MDIO (0x06, 4);
000042  2104              MOVS     r1,#4
000044  2006              MOVS     r0,#6
000046  f7fffffe          BL       output_MDIO
;;;79     
;;;80        /* write PHY address */
;;;81        output_MDIO (PHY_ADDRESS, 5);
00004a  2105              MOVS     r1,#5
00004c  2001              MOVS     r0,#1
00004e  f7fffffe          BL       output_MDIO
;;;82     
;;;83        /* write the PHY register to write */
;;;84        output_MDIO (PhyReg, 5);
000052  2105              MOVS     r1,#5
000054  4620              MOV      r0,r4
000056  f7fffffe          BL       output_MDIO
;;;85     
;;;86        /* turnaround MDO is tristated */
;;;87        turnaround_MDIO ();
00005a  f7fffffe          BL       turnaround_MDIO
00005e  2400              MOVS     r4,#0
000060  4620              MOV      r0,r4
000062  1569              ASRS     r1,r5,#21
                  |L1.100|
000064  0064              LSLS     r4,r4,#1
000066  65a9              STR      r1,[r5,#0x58]
000068  65e9              STR      r1,[r5,#0x5c]
00006a  6d6a              LDR      r2,[r5,#0x54]
00006c  0592              LSLS     r2,r2,#22
00006e  d501              BPL      |L1.116|
000070  f0440401          ORR      r4,r4,#1
                  |L1.116|
000074  1c40              ADDS     r0,r0,#1
000076  2810              CMP      r0,#0x10
000078  d3f4              BCC      |L1.100|
;;;88     
;;;89        /* read the data value */
;;;90        val = input_MDIO ();
;;;91     
;;;92        /* turnaround MDIO is tristated */
;;;93        turnaround_MDIO ();
00007a  f7fffffe          BL       turnaround_MDIO
;;;94     
;;;95        return (val);
00007e  4620              MOV      r0,r4
;;;96     }
000080  bd70              POP      {r4-r6,pc}
;;;97     
                          ENDP

                  mdio_write PROC
;;;98     
;;;99     void mdio_write(int PhyReg, int Value) {
000082  b570              PUSH     {r4-r6,lr}
000084  4604              MOV      r4,r0
;;;100    
;;;101      /* Configuring MDC on P2.8 and MDIO on P2.9 */
;;;102      LPC_GPIO2->FIODIR |= MDIO;
000086  4816              LDR      r0,|L1.224|
000088  460d              MOV      r5,r1                 ;99
00008a  6c01              LDR      r1,[r0,#0x40]
00008c  f4417100          ORR      r1,r1,#0x200
000090  6401              STR      r1,[r0,#0x40]
;;;103    
;;;104      /* 32 consecutive ones on MDO to establish sync */
;;;105      output_MDIO (0xFFFFFFFF, 32);
000092  2120              MOVS     r1,#0x20
000094  f04f30ff          MOV      r0,#0xffffffff
000098  f7fffffe          BL       output_MDIO
;;;106    
;;;107      /* start code (01), write command (01) */
;;;108      output_MDIO (0x05, 4);
00009c  2104              MOVS     r1,#4
00009e  2005              MOVS     r0,#5
0000a0  f7fffffe          BL       output_MDIO
;;;109    
;;;110      /* write PHY address */
;;;111      output_MDIO (PHY_ADDRESS, 5);
0000a4  2105              MOVS     r1,#5
0000a6  2001              MOVS     r0,#1
0000a8  f7fffffe          BL       output_MDIO
;;;112    
;;;113      /* write the PHY register to write */
;;;114      output_MDIO (PhyReg, 5);
0000ac  2105              MOVS     r1,#5
0000ae  4620              MOV      r0,r4
0000b0  f7fffffe          BL       output_MDIO
;;;115    
;;;116      /* turnaround MDIO (1,0)*/
;;;117      output_MDIO (0x02, 2);
0000b4  2102              MOVS     r1,#2
0000b6  4608              MOV      r0,r1
0000b8  f7fffffe          BL       output_MDIO
;;;118      
;;;119      /* write the data value */
;;;120      output_MDIO (Value, 16);
0000bc  2110              MOVS     r1,#0x10
0000be  4628              MOV      r0,r5
0000c0  f7fffffe          BL       output_MDIO
;;;121    
;;;122      /* turnaround MDO is tristated */
;;;123      turnaround_MDIO ();
0000c4  e8bd4070          POP      {r4-r6,lr}
0000c8  f7ffbffe          B.W      turnaround_MDIO
;;;124    }
                          ENDP

                  turnaround_MDIO PROC
;;;37     
;;;38     static void turnaround_MDIO (void) {
0000cc  4804              LDR      r0,|L1.224|
;;;39     
;;;40        /* Turnaround MDO is tristated. */
;;;41        LPC_GPIO2->FIODIR &= ~MDIO;
0000ce  6c01              LDR      r1,[r0,#0x40]
0000d0  f4217100          BIC      r1,r1,#0x200
0000d4  6401              STR      r1,[r0,#0x40]
;;;42        LPC_GPIO2->FIOSET  = MDC;
0000d6  1541              ASRS     r1,r0,#21
0000d8  6581              STR      r1,[r0,#0x58]
;;;43        delay ();
;;;44        LPC_GPIO2->FIOCLR  = MDC;
0000da  65c1              STR      r1,[r0,#0x5c]
;;;45        delay ();
;;;46     }
0000dc  4770              BX       lr
;;;47     
                          ENDP

0000de  0000              DCW      0x0000
                  |L1.224|
                          DCD      0x2009c000
